For example, a load control apparatus for controlling a load such as a lamp or a motor that is mounted in a vehicle is equipped with, for example, a field effect transistor (hereinafter referred to as “FET”) between a battery (DC power supply) and the load, and controls a drive and a stop of the load by switching on and off the FET. Moreover, in order to interrupt the circuit in which the load is connected by quickly detecting an overcurrent when the overcurrent flows through the load, a protection circuit is equipped which switches off the FET when the voltage Vds between the drain and the source of the FET is detected to be increased.
FIG. 3 is a diagram which shows a load drive circuit in which a conventional load control apparatus is equipped. As shown in the figure, in the load drive circuit, an FET (T1: field effect transistor) is provided between a DC power supply VB (shown by the same reference sign VB as the output voltage) and a load RL (the load resistance which the load possesses, as well as the load, are assumed as RL collectively.), and the drive and the stop of the load RL are controlled by switching on and off the FET (T1).
The drain (drain electrode) of the FET (T1) is connected to the plus electrode of the DC power supply VB via a power supply line, and the source (source electrode) of the FET is connected to one end of the load RL via a load line, and the other end of the load RL is connected to the ground.
The power supply line is an electric wire extended from the plus electrode of the DC power supply VB to the drain of the FET (T1), and the load line is an electric wire extended from the source of the FET (T1) to the load RL.
The drain (point P1) of the FET (T1) is connected to the ground through a series circuit of resistances R1 and R2, and the point (P4, voltage V4) where the resistances R1 and R2 are connected is connected to the plus (non-inverting) input terminal of a comparator CMP1.
Further, the minus (inverting) input terminal of the comparator CMP1 is connected to the source (point P2, the voltage V2) of the FET (T1). Thus, when the FET (T1) is switched on and the load RL is driven, the output signal of the comparator CMP1 becomes a level L since the voltage V2 is higher than the voltage V4. Further, when an overcurrent flows to the FET (T1) and the voltage Vds between the drain and the source of the FET (T1) rises because, for example, the load line is grounded, the voltage V2 of the source decreases. Thus, the voltage V2 is lower than the voltage V4, and the output signal of the comparator CMP1 becomes a level H. The output signal is supplied to a driver 11 as an output signal Sout for determining an overcurrent.
The gate (gate electrode) of the FET (T1) is connected to the driver 11 through a gate resistance R3, and a charge pump 12 is connected to the driver 11. Furthermore, the driver 11 is connected to the DC power supply VB through a resistance R4 and is connected to the ground through an input switch SW1. Therefore, when the input switch SW1 is switched off (open circuit), a signal of the level H is input into the driver 11 and the FET (T1) is switched off, and on the other hand, when the input switch SW1 is switched on (closed circuit), a signal of the level L is input into the driver 11 and the FET (T1) is switched on. Further, the FET (T1) is switched off when a signal of the level H (an output signal Sout for determining an overcurrent) is supplied from the comparator CMP1.
Furthermore, between the gate and the source of the FET (T1), a Zener diode ZD1 is provided whose forward direction is a direction from the gate to the source. The voltage between the gate and the source is prevented by the Zener diode ZD1 from exceeding a predetermined voltage.
The power supply line (electric wire extended from the DC power supply VB to the drain of the FET (T1)) shown in FIG. 3 has an inductance component, and the inductance is assumed as Lw1. Similarly, the load line (electric wire extended from the source of the FET (T1) to the load RL) has an inductance component, and the inductance is assumed as Lw2. The resistances of the power supply line and the load line are ignored because they are extremely small.
Here, a capacitor C1 is disposed between the point P1 and the ground (minus electrode of the VB) to prevent the load control apparatus from malfunctioning due to electromagnetic noise that is generated from strong electric waves or various kinds of electrical components (for example, referring to Patent Literature 1).